Cuong Pham The

Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton

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Aggregate all per-module documentation into a single comprehensive IP document

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Generate a design proposal, documentation, and RTL backbone from a requirement file

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Implement Verilog code from an approved design proposal, then lint and simulate

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Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power

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Run all IP-level testcases from tc_list.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions

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Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed

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Generate documentation for any RTL module from Verilog source files

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Scan project state to determine phase completion, write flow_status.md, and orchestrate the full RTL design flow from architecture to documentation

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Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list

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