Results for “hardware”

Document-driven workflow for implementing, reviewing, and verifying Chisel processor and memory-subsystem RTL. Use when Codex must work from maintained Architecture and Design, trace a complete integration surface, reason in synthesized-hardware terms, keep source-adjacent _codex.md summaries current, avoid redundant or overprotective logic, or run focused functional verification.

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Monitor reviewed Grafana telemetry and freshness evidence for IoT devices and edge fleets. Use for smart devices, home automation sensors, remote equipment, wind turbines, space hardware, device-fleet freshness, missing telemetry, and bounded edge-health comparisons.

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Formato GGUF e quantização llama.cpp para inferência eficiente em CPU/GPU. Use ao implantar modelos em hardware de consumidor, Apple Silicon, ou quando precisar de quantização flexível de 2-8 bits sem requisitos de GPU.

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Executa inferência de LLM em CPU, Apple Silicon e GPUs consumer sem hardware NVIDIA. Use para edge deployment, Macs M1/M2/M3, GPUs AMD/Intel ou quando CUDA não está disponível. Suporta quantização GGUF (1,5-8 bits) para redução de memória e aceleração de 4-10× vs PyTorch em CPU.

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Reduza o tamanho de LLMs e acelere a inferência usando técnicas de pruning como Wanda e SparseGPT. Use para comprimir modelos sem retreinamento, alcançando 50% de esparsidade com perda mínima de acurácia, ou ativando inferência mais rápida em aceleradores de hardware. Cobre pruning não estruturado, pruning estruturado, esparsidade N:M, pruning por magnitude e métodos one-shot.

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Judge performance or resource claims on real hardware: benchmark design or review, latency, throughput, memory or headroom numbers, and accept-or-reject decisions on optimizations. Not for refactors with no resource claim.

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Integrate a GPU operator into ATREX with minimal source, compatible lazy APIs, hardware dispatch, atrex-prefixed kernels, one functional test file, and target-GPU validation.

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Implement or extend a reusable hardware chip and its machine-specific wiring in EMULATORS, including registers, pins or logical signals, clocks, state machines, memory-mapped behavior, side effects, interrupts, DMA or bus requests, serialization, introspection, and chip tests. Use when adding a controller, timer, PIA, PPI, UART, video or sound device, custom ASIC, register bank, or a variant of an existing chip.

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Validate and implement Sinclair ZX Spectrum 16K/48K ULA and board-level behavior in the EMULATORS repository, including PAL/NTSC raster timing, bitmap and attribute fetches, FLASH/BRIGHT/INK/PAPER rendering, CPU clock generation, lower-RAM and I/O contention, floating bus, snow effect, DRAM addressing and refresh, port FE keyboard/tape/border/sound behavior, interrupts, and ULA revision boundaries. Use when Codex reviews or edits namespace ZXSPECTRUM ULA, ULARegisters, Memory, PortManager, Screen, Sound, Datasette, Z80 bus timing, raster, contention, or ZX Spectrum hardware tests.

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Validate and implement Sinclair ZX Spectrum 48K ROM-visible behavior in the EMULATORS repository, including reset and restart vectors, IM1/NMI handling, keyboard scanning and repeat, beeper and tape routines, screen/printer output, channels and streams, BASIC tokenization and execution, expression evaluation, memory movement, system variables, calculator stack, floating-point formats, ROM traps, localized ROM selection, and firmware/hardware timing contracts. Use when Codex reviews or edits ZX Spectrum ROM loading, KERNAL-style traps, keyboard, tape, screen, printer, BASIC files, tokens, system variables, startup, interrupts, or compatibility tests.

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Design and implement unit, conformance, integration, timing, boot, trace, video, audio, and regression tests for EMULATORS processors, chips, peripherals, and complete machines. Use when creating a verification strategy for a new emulator, converting hardware documentation into tests, adding diagnostic programs or golden artifacts, measuring behavioral coverage, or proving that components interact correctly.

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Plan, scaffold, implement, and integrate a complete new emulated computer or console in the EMULATORS repository. Use when Codex creates a new machine, platform, hardware model, or emulator executable; decides which existing CPUs, chips, memory, I/O, video, sound, ROM, and framework classes to reuse or extend; or coordinates several emulator subsystems into a bootable tested system.

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Generate formal IT/hardware purchase request documents from informal requirements. Use when creating purchase justifications, cost-benefit analyses, ROI calculations, vendor comparisons, or MARP presentation slides for management approval.

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Detect bootkits such as BlackLotus and Bootkitty and Secure Boot bypass via DBX and binary checks.

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Use Intel CHIPSEC to assess platform firmware configuration, SPI flash write protection, BIOS lock, SMM/SMRR, and Secure Boot variable state, dump SPI flash, and triage UEFI variables for firmware-level threats.

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Complete SolanaOS agent skill — install, configure, and operate the autonomous Solana trading runtime with Honcho v3 epistemological memory, multi-venue perp trading (Hyperliquid + Aster), on-chain intelligence with USD pricing, Telegram bot, gateway API, Tailscale mesh, hardware integration, and cross-session recall. Use when asked to install SolanaOS, query Solana blockchain data, manage wallets, run OODA trading loops, configure strategies, control BitAxe mining fleets, pair Seeker devices, or operate any SolanaOS runtime surface.

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Use when developing, reviewing, debugging, porting, or engineering Linux kernel device drivers, kernel modules, device tree bindings, bus clients, subsystem drivers, DMA/IRQ/memory paths, userspace interfaces, or hardware bring-up plans.

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Use when designing, reviewing, modifying, migrating, optimizing, securing, operating, troubleshooting, or decommissioning data architectures across data model exploration, SQL, ISO SQL conformance, NoSQL, vector, graph, document, time-series, NewSQL, search, in-memory, SQLite, CDC/Debezium, DBMS storage/query/recovery internals, database incident prevention, hardware acceleration, cache, big-data, lakehouse, and warehouse systems.

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Topics on Secure Hardware, Fall 2018 Decentralized Technologies Decentralized Finance MOOC, Fall 202

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I-A LLMs Large Language Models (LLMs) are extensive, general-purpose models that can be pre-trained and adapted for specific tasks.

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Maintain IT asset inventory and configuration management database. Track hardware, software, and cloud resources. Use when managing IT assets.

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Migrate a .NET 10 project or solution to .NET 11 and resolve all breaking changes. This is a MIGRATION skill — use it when upgrading from .NET 10 to .NET 11, NOT for writing new programs. USE FOR: upgrading TargetFramework from net10.0 to net11.0, fixing build errors after updating the .NET 11 SDK, resolving source-breaking and behavioral changes in .NET 11 runtime, C# 15 compiler, and EF Core 11, adapting to updated minimum hardware requirements (x86-64-v2, Arm64 LSE), and updating CI/CD pipelines and Dockerfiles for .NET 11. DO NOT USE FOR: .NET Framework migrations, upgrading from .NET 9 or earlier, greenfield .NET 11 projects, or cosmetic modernization unrelated to the upgrade. NOTE: .NET 11 is in preview. Covers breaking changes through Preview 3.

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Documentation structure and maintenance rules for the Megahub project. Use whenever making user-facing changes — adding features, changing behavior, fixing hardware compatibility, or modifying configuration. Describes which files to update, the README structure, and writing style.

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FlutterSecureStorage (v10.x) for encrypted key-value storage of sensitive data using platform-native secure enclaves with biometric authentication support. Use this skill when storing OAuth tokens (access tokens, refresh tokens, ID tokens), API keys and secrets, user passwords or PINs, session tokens, encryption keys, private keys for cryptography, certificate data, biometric enrollment data, banking credentials, health data, or any sensitive information requiring platform-level encryption (iOS Keychain with Secure Enclave, Android Keystore with Hardware-backed keys). Supports Touch ID, Face ID, and Android biometric prompt integration. Handles biometric change invalidation (resetOnError), data migration from SharedPreferences/EncryptedSharedPreferences, Google Drive backup exclusion, automatic key rotation, configurable encryption algorithms (AES), and prevents data extraction even on rooted/jailbroken devices. Essential for authentication flows, secure credential management, or compliance requirements (PCI DSS, HIPAA, GDPR data protection).

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