'hardware' 검색 결과

Visual design audit for iOS apps on real hardware. (gstack)

한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.

Bench instruments and measurement techniques for electronics — digital multimeter, oscilloscope, logic analyzer, spectrum analyzer, function generator, power supply, and their proper use. Covers probing technique, ground loops, loading effects, trigger modes, FFT mode pitfalls, signal integrity, noise budget analysis, and debugging workflows from "it doesn't work" to "here is the failure mechanism." Use when measuring, debugging, or characterizing any electronic circuit or firmware-hardware interaction.

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Embedded firmware development for microcontrollers including memory-mapped I/O, GPIO, interrupts, timers, UART/SPI/I2C serial protocols, PWM generation, ADC sampling, interrupt-driven versus polled architectures, RTOS fundamentals, and the bring-up sequence from power-on reset through first printf. Covers AVR/Arduino, ARM Cortex-M, and ESP32 patterns. Use when writing, porting, debugging, or reviewing firmware that directly manipulates hardware peripherals.

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Systems programming from memory management through networking. Covers memory models (stack vs heap, manual allocation, garbage collection, ownership/borrowing), concurrency (threads, mutexes, channels, async/await, actor model, data races vs race conditions), operating system concepts (processes, virtual memory, page tables, system calls, file descriptors, signals), compilation (lexing, parsing, code generation, linking, static vs dynamic libraries), networking fundamentals (TCP/IP, sockets, HTTP, DNS, TLS), and the hardware-software boundary (caches, cache lines, false sharing, memory-mapped I/O). Use when working with low-level code, diagnosing system-level bugs, understanding performance characteristics, or bridging between high-level languages and machine behavior.

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Computational thinking as a problem-solving discipline independent of programming languages. Covers the four pillars (decomposition, pattern recognition, abstraction, algorithm design), computational problem-solving methodology (understand, decompose, generalize, formalize, verify), abstraction levels (from hardware through user interface), modeling and simulation, automata and formal languages (DFA, NFA, regular expressions, context-free grammars, Turing machines), computational complexity classes (P, NP, NP-complete, undecidable), and constructionist pedagogy (learning by building, Logo, Scratch, physical computing). Use when approaching unfamiliar problems, teaching problem-solving strategies, analyzing problem complexity, or bridging between domain knowledge and computational solutions.

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Understanding how digital systems actually work -- hardware, operating systems, networks, and information representation -- at a depth sufficient to reason about them rather than just use them. Covers CPU/RAM/storage/GPU roles, what an OS does, how packets travel the internet, and how computers represent numbers, text, images, and sound as binary. Use when a learner needs to build a mental model of computing rather than memorize menu paths.

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Integration of advanced IoT protocols for Zephyr RTOS. Covers OpenThread mesh networking, Matter-over-Thread device development, Golioth Cloud SDK patterns, and LoRaWAN basics. Trigger when building smart home devices, wide-area sensor networks, or cloud-integrated hardware fleets.

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Essential Zephyr RTOS kernel services. Covers thread lifecycle and priority, the logging subsystem for diagnostics, and the interactive shell for real-time hardware inspection and debugging. Trigger when writing application flows, adding logging to modules, or creating interactive CLI commands.

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Specialized hardware interfaces and system reliability for Zephyr RTOS. Covers LVGL GUI development, Audio I2S/Codecs, Watchdog timers, and Fault Injection. Trigger when building human-machine interfaces (HMI), audio devices, or high-reliability mission-critical systems.

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Host-based simulation using the Zephyr native_sim board. Covers building for Linux/macOS/Windows, automated testing, host-side debugging (GDB, Valgrind), and host-target integration. Trigger when developing application logic without hardware or setting up CI/CD tests.

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Foundational skills for Zephyr RTOS development. Covers essential Embedded C patterns (BIT, CONTAINER_OF), real-time concurrency primitives (mutexes, semaphores, spinlocks), hardware literacy (datasheet-to-DTS mapping), and defensive programming. Trigger when writing core application logic, drivers, or troubleshooting foundational behavior.

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USB and CAN connectivity for Zephyr RTOS. Covers USB device stack configuration (CDC ACM, HID, MSC), CAN controller integration, and professional USB-to-CAN adapter patterns including buffering and protocol packetization. Trigger when adding USB interfaces, implementing CAN bus communication, or building hardware diagnostic tools.

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Quantum computing framework for building, simulating, optimizing, and executing quantum circuits. Use this skill when working with quantum algorithms, quantum circuit design, quantum simulation (noiseless or noisy), running on quantum hardware (Google, IonQ, AQT, Pasqal), circuit optimization and compilation, noise modeling and characterization, or quantum experiments and benchmarking (VQE, QAOA, QPE, randomized benchmarking).

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OCRs scanned or image-only corpora with vision-language models in four phases. Triage inventories the scans, identifies script and language, and shortlists models by script, hardware, and data constraints. Evaluate selects a system by measured CER or WER against ground truth, using born-digital twins, a second reader, and decision rules set in advance. Run builds the production pipeline. Clean removes model artifacts, audits what every cleaning rule deletes, corrects with rule-based and LLM passes, and records provenance. Use when choosing an OCR model for a corpus, measuring OCR accuracy, transcribing scans at scale, or correcting raw OCR. Born-digital documents with text layers go to doc-to-markdown; runs on Leiden's ALICE cluster add vlm-ocr-alice.

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OCR scanned or image-only corpora with vision-language models in four phases: `triage` inventories the scans, identifies script and language, and shortlists models by script, hardware, and data constraints; `evaluate` picks a system by measured CER/WER against ground truth, using born-digital twins, a second reader, and decision rules set in advance; `run` builds the production pipeline; and `clean` removes model artifacts, audits what every cleaning rule deletes, corrects with rule-based and LLM passes, and records provenance. Born-digital documents with a text layer go to $doc-to-markdown; runs on Leiden's ALICE cluster add $vlm-ocr-alice.

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Use when the user wants to run a diffusers pipeline from a terminal (one-off generation, batch jobs, smoke-testing a new model), run on HF Sandbox hardware via `--remote`, introspect a pipeline's input schema before calling it, or attach a LoRA at inference time. Prefer this over writing ad-hoc Python scripts for generation tasks.

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Use whenever the user wants to find, shortlist, vet, or enrich US B2B law firms — corporate, IP/patent, M&A and securities, employment, commercial litigation, regulatory/compliance, data privacy/cyber, real estate, and tax. Triggers on "find three boutique IP law firms in California", "shortlist M&A counsel for a Series-B fundraise", "patent prosecution for our hardware startup", or "pull contact info for these 10 law firm domains", even when described indirectly (outside counsel, cap-table review, GDPR/SOC2 oversight). Drives the ServiceGraph API (api.servicegraph.co) — a 100k+ US firm catalog filterable by industry, services, location, size, ratings. Skip personal/consumer legal services where the user is the end client (divorce, personal injury, criminal defense, family law, estate planning, wills) — the catalog is B2B-only. Also skip in-house GC hires, "is this NDA enforceable" DIY questions, non-US firms, individual freelancers.

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Use whenever the user wants to find, shortlist, vet, or enrich US software development firms — custom software, web development, mobile app development, backend/API development, DevOps/cloud, system integration, and hosting. Triggers on "find a software dev shop in Austin", "shortlist three custom-software firms with healthcare experience", "we need a mobile app developer for our iOS launch", or "pull contact info for these 10 dev shop domains", even when described indirectly (build a tool, ship a feature, technical partner). Drives the ServiceGraph API (api.servicegraph.co) — a 100k+ US firm catalog filterable by industry, services, location, size, ratings. Defer to find-web-developer for strictly website/landing-page projects. Defer AI/ML, ML pipelines, model building, and data-engineering asks — those are a sibling industry, not software development. Skip in-house engineer hires, code-writing/debugging tasks, cloud-product comparisons, hardware/civil engineering, non-US firms, individual freelancers.

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Use for every hardware bring-up or debug session that ports mainline Linux to a phone or tablet. Retail-unlock targets require an already-unlocked bootloader; locked retail bootloaders are out of scope. Exploit-booted and firmware-booted targets require a demonstrated boot path; the skill never provides unlock or exploit steps.

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Scout ONE external surface of the TouchDesigner community for what's HYPED in 2025-2026 that could become a tdmcp tool. Use when a td-trend-scout sub-agent is assigned a surface (community-showcase, tutorials, generative-ai, hardware-interactive, or vfx-aesthetics) during the tdmcp-hype-scout harness — produces `_workspace/hype-scout/01_scout_<surface>.md` with cited trend candidates ranked by hype intensity, recency, and build-ease in tdmcp.

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Scout the TouchDesigner community for what's HYPED right now — community showcases, recent tutorials, generative-AI bridges, hardware interaction trends, visual-aesthetic trends of 2025-2026 — then propose tdmcp tools that ride those trends AND are easy to build. Use whenever the user wants to brainstorm new feature ideas based on what's trending in TouchDesigner, asks for 'hype' or 'trending' features, asks 'what are people doing in TD right now / what's hot / what's hype', wants tools inspired by community trends, asks to scout TD trends/aesthetics/integrations, or says things like 'ideias hype', 'novas ideias', 'o que está em alta', 'criar ferramentas para o que está bombando', 'tendências do TouchDesigner'. Also for follow-ups: refresh, rescout one surface, re-rank under another profile, deepen a trend, or filter for buildable-easy items. This is an EXTERNAL trend ideation harness — complementary to tdmcp-feature-discovery (which is INTERNAL gap analysis). It produces `_workspace/hype-scout/HYPE_TOOL_BACKLOG.md` ranked by Hype × Build-Ease; it does NOT build. Once a feature is chosen from the backlog, hand it to tdmcp-pipeline.

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Look at real hardware, screens, panels, and wiring on a desk or workbench through a camera, so Claude can SEE physical output that no unit test, log, or API can. Use whenever the user says "are you seeing this?", "olha isso", "look at this", "watch this", "can you see...", "check the camera", "look at the screen" / "look at the display", "is this wired right?", or "what's this part?"; asks to visually verify a rendered display, LCD, LED, or panel; wants a wiring, polarity, or voltage-rail check before power-on; or needs to confirm a font, layout, clipping, or on-screen value renders correctly instead of trusting green tests. Grabs the current camera frame(s) and reads them; supports a watch mode for an action in progress. Needs a snapshot-capable camera reachable over HTTP (Android IP Webcam app, Raspberry Pi camera-streamer, or any snapshot URL) set via CCE_CAM_URL.

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Forecast infrastructure and application metrics using Prophet or statsmodels for capacity planning, cost optimization, and proactive scaling. Visualize predictions in Grafana and set up alerts for projected resource exhaustion. Use when forecasting infrastructure capacity needs for CPU, memory, or disk, planning hardware procurement for next quarter, predicting cost trends to optimize cloud spending, or setting up proactive scaling policies based on predicted load.

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Design combinational logic circuits from a functional specification through gate-level implementation. Covers AND, OR, NOT, XOR, NAND, NOR gates; NAND/NOR universality conversions; and standard building blocks including multiplexers, decoders, half/full adders, and ripple-carry adders. Use when translating a Boolean function or truth table into a hardware-realizable gate network and verifying it by exhaustive simulation.

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