Build and verify a vendor-neutral PCB/PCBA manufacturing release from one frozen design revision. Use when generating or auditing Gerber, drill, IPC-2581/ODB++, BOM, CPL/pick-and-place, assembly drawings, constraints, renders, DFM evidence, hashes, or release manifests, and when preventing mixed-revision fabrication or assembly uploads.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
설치 방법 보기설치하기 전에 에이전트에게 전달되는 지시 내용을 확인할 수 있습니다.
Release artifacts; do not redesign the circuit or layout inside this stage. Read references/release-checklist.md and references/eda-release-adapters.md.
Use the authoritative EDA tool to export all applicable layers, solder mask, paste, silkscreen, outline/cutouts, mechanical information, plated/non-plated drill, drill map/report, BOM, CPL, assembly drawings, stackup/impedance notes, and top/bottom renders. Preserve units, origin, side convention, rotation convention, DNP policy, polarity, and pin-1 evidence.
Inspect the generated files in an independent Gerber/assembly viewer. Compare outline and dimensions, layer count, copper/mask, drills, text, apertures, keepouts, edge treatments, panel/depanel needs, and assembly side. Export a via/drill histogram and identify every feature below the current standard-cost process threshold.
Build .pcba-workflow/release-manifest.json with
scripts/build_release_manifest.py. Supply an explicit revision for every
artifact; the script rejects mixed revisions. Record:
Run scripts/validate_release_manifest.py after moving or packaging the
release. A missing file, hash drift, mixed revision, stale sourcing lock, or
failed required check blocks release.
In a recorded workflow, append checkpoints for the frozen source revision, independent Gerber/drill inspection, BOM/CPL reconciliation, renders, and the validated release manifest. Promotion frames may show sanitized viewers, but the machine-readable release and hashes remain the approval evidence.
Deliver an immutable release directory containing the manifest, manufacturing
files, assembly files, constraints, and review evidence. State the exact upload
Gerber/archive, BOM, and CPL. Hand live supplier interpretation to
$operate-jlcpcb-order; it must not silently repair this release.
아직 리뷰가 없습니다. 사용해 본 소감을 남겨 주세요.
로그인 없이 쓸 수 있습니다. 사용 후기, 질문, 작동하지 않은 환경 등을 편하게 남겨 주세요.
아직 댓글이 없습니다. 첫 댓글을 남겨 보세요.
Design, audit, or correct an electronic circuit from a product brief, native schematic, netlist, block diagram, or circuit description. Use for architecture and component-function review, power and logic-domain checks, reset and boot sequencing, bus ownership, ratings, timing, protection, safe states, component suitability, circuit bugs, or layout-facing electrical constraints.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Coordinate an evidence-gated electronic product and PCBA workflow from an idea, circuit description, schematic, netlist, PCB, BOM, or fabrication package through a reviewed order. Use for end-to-end requests, multi-stage hardware projects, workflow recovery, gate tracking, change invalidation, or deciding which specialist skill is required next.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Operate and review a JLCPCB PCB/PCBA quote, optional physical-stencil request, or order using a frozen Gerber/drill, BOM, CPL, sourcing lock, constraints, and release manifest. Use for browser upload, board or stencil options, cost anomalies, coupons, component matching, substitutions, imported placement calibration, top/bottom preview inspection, cart preparation, or order records without silently accepting placement errors or payment.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Audit, finish, or port PCB placement and routing using circuit intent, mechanical constraints, sourcing evidence, native DRC/connectivity, rendered views, and manufacturing feedback. Use before routing, after autorouting, before fabrication release, when adapting a proven board to another connector, enclosure, platform, or regional variant, or when reviewing layers, GND references, power distribution, decoupling, buses, controlled interfaces, RF keepouts, vias, cost-driving features, opens, or DRC findings.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Turn an electronic product idea, behavior description, reverse-engineering note, or incomplete circuit concept into a decision-ready engineering brief and architecture. Use before schematic design or audit when functions, operating states, power, interfaces, mechanics, production quantity, cost, or measurable requirements are missing or ambiguous.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Verify a PCBA BOM and proposed components before circuit or placement freeze, including exact manufacturer part numbers, pin semantics, packages, footprints, CAD and 3D models, lifecycle, live stock, MOQ, assembly class, price, and approved substitutes. Use for sourcing locks, unavailable or expensive parts, JLCPCB/LCSC matching, BOM risk, or cost-aware substitution decisions.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.