Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
설치 방법 보기설치하기 전에 에이전트에게 전달되는 지시 내용을 확인할 수 있습니다.
ERC and DRC cannot catch a swapped pin. A power pin on a signal net passes all automated checks but produces a dead or damaged board. The only defense is comparing the schematic pin-to-net assignment against the datasheet pinout table.
# scripts/pin_maps.py
DEVICE_PINMAP = {
"A1": "GND",
"A2": "VDD_1V8",
"A3": "SPI_CLK",
"B1": "RESET_N",
"C4": "__NC__", # explicitly no-connect
}
Sources (in priority order):
kicad skill and retain the per-component
pin/net data as analysis.json.scripts/audit_pinmap.py
exists.Unmapped pins should get no-connect markers rather than floating unconnected. Floating digital inputs can cause latch-up or undefined behavior.
Flag any IC below 80% mapped. No-connect pins count as mapped.
| IC ref | Package | Total pins | Mapped | NC | Coverage |
|---|---|---|---|---|---|
| (fill in) |
SOT-23 transistors: BCE, BEC, EBC, and CBE orderings all exist for NPN BJTs;
GDS, GSD, SGD for N-MOSFETs. The KiCad symbol lib_id suffix encodes an assumed
pinout. Verify against the actual MPN's datasheet -- especially when no MPN is set.
Multi-unit ICs: Op-amp and gate packages with a shared VCC/GND unit. Ensure the power unit is placed and connected -- a missing power unit causes an ERC warning that can be overlooked.
Active-low signals: Verify RESET_N, CS_N, OE_N are driven with the correct polarity. A high-true signal on an active-low input means always-asserted.
아직 리뷰가 없습니다. 사용해 본 소감을 남겨 주세요.
로그인 없이 쓸 수 있습니다. 사용 후기, 질문, 작동하지 않은 환경 등을 편하게 남겨 주세요.
아직 댓글이 없습니다. 첫 댓글을 남겨 보세요.
Route non-critical nets on a real KiCad PCB or Specctra DSN through Circuit Weaver's fail-closed Freerouting integration. Use after placement and net-class setup when the user requests autorouting, a validated SES session, routing diagnostics, or post-route cleanup. Keep critical power, RF, clock, crystal, switching, and differential nets manual.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Manage an electronics bill of materials across distributors and fabricators: part selection, stock, pricing, alternates, ordering, KiCad properties, and BOM/CPL export. Use for distributor-neutral sourcing, cost comparison, order preparation, or requests such as "what parts do I need" and "export for JLCPCB". Do not take over schematic analysis or a complete new-design workflow unless the requested task is specifically its sourcing/manufacturing stage.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
BOM management, sourcing, pricing, export, and fabrication preparation. Load the canonical Circuit Weaver skill from `skills/bom/SKILL.md`.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Create, import, analyze, resume, or revise an end-to-end Circuit Weaver electronic design from requirements through validated functional KiCad schematics, placement review, and a truthful manufacturing handoff. Use for new designs and for existing KiCad/PCB/Gerber projects that need durable state. Use kicad for one-off file inspection, bom for standalone sourcing, and design-wizard only when the user explicitly requests the slower questionnaire.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.
Use only for an explicitly requested step-by-step Circuit Weaver questionnaire. Load the canonical workflow from skills/design-wizard/SKILL.md; use circuit-weaver for ordinary automatic new-design requests.
한국어 요약은 준비 중입니다. 원문 설명을 표시하고 있습니다.