Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.
インストールする前に、エージェントに与えられる指示の中身を確認できます。
ERC and DRC cannot catch a swapped pin. A power pin on a signal net passes all automated checks but produces a dead or damaged board. The only defense is comparing the schematic pin-to-net assignment against the datasheet pinout table.
# scripts/pin_maps.py
DEVICE_PINMAP = {
"A1": "GND",
"A2": "VDD_1V8",
"A3": "SPI_CLK",
"B1": "RESET_N",
"C4": "__NC__", # explicitly no-connect
}
Sources (in priority order):
kicad skill and retain the per-component
pin/net data as analysis.json.scripts/audit_pinmap.py
exists.Unmapped pins should get no-connect markers rather than floating unconnected. Floating digital inputs can cause latch-up or undefined behavior.
Flag any IC below 80% mapped. No-connect pins count as mapped.
| IC ref | Package | Total pins | Mapped | NC | Coverage |
|---|---|---|---|---|---|
| (fill in) |
SOT-23 transistors: BCE, BEC, EBC, and CBE orderings all exist for NPN BJTs;
GDS, GSD, SGD for N-MOSFETs. The KiCad symbol lib_id suffix encodes an assumed
pinout. Verify against the actual MPN's datasheet -- especially when no MPN is set.
Multi-unit ICs: Op-amp and gate packages with a shared VCC/GND unit. Ensure the power unit is placed and connected -- a missing power unit causes an ERC warning that can be overlooked.
Active-low signals: Verify RESET_N, CS_N, OE_N are driven with the correct polarity. A high-true signal on an active-low input means always-asserted.
まだレビューはありません。使ってみた感想をお寄せください。
概要と使いどころ
Route non-critical nets on a real KiCad PCB or Specctra DSN through Circuit Weaver's fail-closed Freerouting integration. Use after placement and net-class setup when the user requests autorouting, a validated SES session, routing diagnostics, or post-route cleanup. Keep critical power, RF, clock, crystal, switching, and differential nets manual.
日本語の概要は準備中です。原文の説明を表示しています。
BOM management, sourcing, pricing, export, and fabrication preparation. Load the canonical Circuit Weaver skill from `skills/bom/SKILL.md`.
日本語の概要は準備中です。原文の説明を表示しています。
Manage an electronics bill of materials across distributors and fabricators: part selection, stock, pricing, alternates, ordering, KiCad properties, and BOM/CPL export. Use for distributor-neutral sourcing, cost comparison, order preparation, or requests such as "what parts do I need" and "export for JLCPCB". Do not take over schematic analysis or a complete new-design workflow unless the requested task is specifically its sourcing/manufacturing stage.
日本語の概要は準備中です。原文の説明を表示しています。
Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.
日本語の概要は準備中です。原文の説明を表示しています。
Create, import, analyze, resume, or revise an end-to-end Circuit Weaver electronic design from requirements through validated functional KiCad schematics, placement review, and a truthful manufacturing handoff. Use for new designs and for existing KiCad/PCB/Gerber projects that need durable state. Use kicad for one-off file inspection, bom for standalone sourcing, and design-wizard only when the user explicitly requests the slower questionnaire.
日本語の概要は準備中です。原文の説明を表示しています。
Run the explicit, human-in-the-loop Circuit Weaver questionnaire from requirements through a validated design and KiCad handoff. Use only when the user asks for the design-wizard skill, the offline interactive wizard, or a slow step-by-step guided questionnaire. Do not trigger for ordinary new-design requests; use circuit-weaver for automatic end-to-end orchestration.
日本語の概要は準備中です。原文の説明を表示しています。