“systemverilog”的搜索结果

资深RTL设计工程师，根据微架构文档（MAS、FSM、datapath）编写可综合的 SystemVerilog HDL代码。Generate synthesizable SystemVerilog RTL from MAS documents. Trigger: /bb-rtl-coder, RTL实现, SystemVerilog代码, 可综合HDL

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Automatically infer formal correctness properties from Verilog/SystemVerilog RTL code and generate SystemVerilog Assertions (SVA). Identifies control-flow invariants (mutual exclusion, valid-ready handshakes, pipeline ordering, safety properties), liveness expectations, and temporal properties. Use when working with RTL designs that need formal property generation, when adding assertions to existing RTL, or when users ask to infer properties, generate assertions, or create formal specifications from hardware designs.

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Choose or explain HSB Sensor RX packetizer fields for HOLOLINK_def.svh. Do not use for full defs, validation, or runtime APB programming.

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Generate, validate, compare, or explain HSB HOLOLINK_def.svh macros. Do not use for FPGA_top.sv wrappers or packetizer-only derivation. Generation runs bundled Python scripts locally through shell commands and writes validated .svh output files after user-confirmed paths.

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Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.

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Check behavioral consistency between high-level hardware specifications and RTL implementations. Use when asked to check RTL consistency, verify RTL against spec, check hardware specification compliance, validate RTL implementation, find spec violations in RTL, check behavioral consistency, or when working with hardware designs that need verification against protocol specifications, timing requirements, or functional specifications in Verilog, VHDL, or SystemVerilog.

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Think and work like an expert Computer Hardware Engineer. Use when a task calls for Computer Hardware Engineer judgment. Reasons from CPI/AMAT and MESI/MOESI coherence through SystemVerilog RTL, PrimeTime/Design Compiler/Innovus signoff, PCIe LTSSM/TLP, SVA formal, and clock-gating power while treating CDC metastability, false-path abuse, X-optimism, and coherency traffic as first-class failure modes.

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解析 SystemVerilog RTL 为 AST JSON，供 CDC 检查 / signal path tracing / module dep 分析。统一 4 个后端 (babel-lsp / pyverilog / verible / slang)，auto 模式自动降级。触发场景：(1) bba-guru-synthesis CDC 前；(2) bb-trace-signal-path / bb-find-module-deps 之前；(3) 显式 /bb-parse-ast。

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根据 MAS + verification_plan + RTL 接口描述生成 SystemVerilog UVM 或 cocotb 测试平台与 test cases 清单。触发场景：(1) bba-guru-verification 在 plan 完成后；(2) 补充 corner case TB；(3) 显式 /bb-generate-tb。

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