<一句话说清『这个 skill 做什么 + 何时调用』。把最关键的触发场景放最前面。结尾给 2-3 个用户会说的关键词。
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See how to installReview the instructions the agent will receive before you install.
单行用途描述。
| 参数 | 类型 | 说明 |
|---|---|---|
| arg1 | string | … |
<期望输出格式，markdown / json / 文件>
references/<file>.md：<说明>scripts/<file>.sh：<说明>examples/<file>：<说明>| 场景 | 处理 |
|---|---|
| 输入缺字段 | escalate-user，不要猜测 |
| 工具失败 | 重试 ≤ N 次，仍失败则记录到 .handoff/ |
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从粗略 idea 设计芯片或功能模块架构，输出专业架构文档到 spec_arch 目录。Trigger: 芯片架构设计, IC架构, 电路模块设计, 硬件架构. Generate IC/Chip architecture specification from rough ideas.
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基于 AST 检查 CDC/RDC 违例：对比 MAS clock_domains 找跨域信号，检查是否被 2ff-sync CBB 保护。触发场景：(1) bba-guru-synthesis 综合前；(2) 显式 /bb-check-cdc。
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调用 babel-lsp / verible-verilog-lint 检查 SV 源码。src 必须可综合（零 syntax error），tb 允许 verification constructs。发现 src error 时自动修复重检（max 3 iter）。触发：(1) bba-guru-rtl 生成后；(2) RTL 修复重检；(3) 显式 /bb-check-lint。
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Babel internal issue protocol — close a handoff after downstream agent picked it up or user signed off. Moves designs/<name>/.handoff/<label>.md to .handoff/closed/ (using mv per CLAUDE.md), appends to handoff_log.jsonl.
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对抗性代码评审：代码质量 / 可维护性 / 时序风险 / 综合友好度 / MAS 对齐度。默认 ruthless 模式，找 EVERY flaw。触发场景：(1) RTL lint 后；(2) 显式 /bb-code-review。
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解析 Verilator coverage.dat + sim log，输出 functional + code coverage 数值，判断是否 100% 达标。触发场景：(1) bb-invoke-verilator 后；(2) 每次回归后；(3) 显式 /bb-collect-coverage。
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