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Prepare a defense-contractor environment for CMMC Level 2 certification: scope CUI and FCI, implement the 110 NIST SP 800-171 Rev 2 security requirements across 14 families, compute the SPRS score with the DoD Assessment Methodology, manage a compliant POA&M, and ready the organization for a C3PAO assessment. Use when an organization handles Controlled Unclassified Information (CUI) under a DoD contract, when a contract carries DFARS clause 252.204-7012/7019/7020/7021, when preparing for or responding to a CMMC assessment, when computing or improving an SPRS score, when building a System Security Plan or POA&M for 800-171, or when scoping which systems are in the CUI boundary. Keywords: CMMC, CMMC Level 2, NIST 800-171, SP 800-171 Rev 2, CUI, FCI, SPRS, DFARS 7012, C3PAO, POA&M, System Security Plan, DoD Assessment Methodology, 110 controls, defense industrial base, DIB, FedRAMP equivalency.

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Run automatic SPICE simulations on subcircuits detected from KiCad schematic analysis — validates filter frequencies, divider ratios, opamp gains, LC resonance, and crystal load capacitance. Supports ngspice, LTspice, and Xyce (auto-detected). Generates testbenches, runs batch mode, produces structured pass/warn/fail report. Use when the user asks to simulate, verify, or validate any analog subcircuit — RC filters, LC filters, voltage dividers, opamp circuits, crystal oscillators. Also for "simulate my circuit", "run spice", "verify with simulation", "check my filter cutoff", "does this divider give the right voltage", "what's the bandwidth of this opamp stage". Consider suggesting simulation during design reviews when the schematic analyzer reports simulatable subcircuits and a SPICE simulator is available.

日本語の概要は準備中です。原文の説明を表示しています。

Run automatic SPICE simulations on subcircuits detected from KiCad schematic analysis — validates filter frequencies, divider ratios, opamp gains, LC resonance, and crystal load capacitance. Supports ngspice, LTspice, and Xyce (auto-detected). Generates testbenches, runs batch mode, produces structured pass/warn/fail report. Use when the user asks to simulate, verify, or validate any analog subcircuit — RC filters, LC filters, voltage dividers, opamp circuits, crystal oscillators. Also for "simulate my circuit", "run spice", "verify with simulation", "check my filter cutoff", "does this divider give the right voltage", "what's the bandwidth of this opamp stage". Consider suggesting simulation during design reviews when the schematic analyzer reports simulatable subcircuits and a SPICE simulator is available.

日本語の概要は準備中です。原文の説明を表示しています。

Expert-level circuit analysis covering KVL, KCL, nodal and mesh analysis, Thevenin and Norton theorems, AC circuits, phasors, and frequency response.

日本語の概要は準備中です。原文の説明を表示しています。

Prepare a defense-contractor environment for CMMC Level 2 certification: scope CUI and FCI, implement the 110 NIST SP 800-171 Rev 2 security requirements across 14 families, compute the SPRS score with the DoD Assessment Methodology, manage a compliant POA&M, and ready the organization for a C3PAO assessment. Use when an organization handles Controlled Unclassified Information (CUI) under a DoD contract, when a contract carries DFARS clause 252.204-7012/7019/7020/7021, when preparing for or responding to a CMMC assessment, when computing or improving an SPRS score, when building a System Security Plan or POA&M for 800-171, or when scoping which systems are in the CUI boundary. Keywords: CMMC, CMMC Level 2, NIST 800-171, SP 800-171 Rev 2, CUI, FCI, SPRS, DFARS 7012, C3PAO, POA&M, System Security Plan, DoD Assessment Methodology, 110 controls, defense industrial base, DIB, FedRAMP equivalency.

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Build sequential (stateful) logic circuits including latches, flip-flops, registers, counters, and finite state machines. Covers SR latch, D and JK flip-flops, binary/BCD/ring counters, and Mealy/Moore FSM design with clock signal and timing analysis. Use when a circuit must remember past inputs, count events, or implement a state-dependent control sequence.

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Design, audit, or correct an electronic circuit from a product brief, native schematic, netlist, block diagram, or circuit description. Use for architecture and component-function review, power and logic-domain checks, reset and boot sequencing, bus ownership, ratings, timing, protection, safe states, component suitability, circuit bugs, or layout-facing electrical constraints.

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Breadboard circuit mockups via HTML5 Canvas. Use when creating circuit layouts, visualizing 6502/retro electronics components, drawing breadboard diagrams, or designing vintage computer schematics with discrete parts.

日本語の概要は準備中です。原文の説明を表示しています。

Generate breadboard circuit mockups and visual diagrams using HTML5 Canvas drawing techniques. Use when asked to create circuit layouts, visualize electronic component placements, draw breadboard diagrams, mockup 6502 builds, generate retro computer schematics, or design vintage electronics projects. Supports 555 timers, W65C02S microprocessors, 28C256 EEPROMs, W65C22 VIA chips, 7400-series logic gates, LEDs, resistors, capacitors, switches, buttons, crystals, and wires.

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Create data fetching services with circuit breaker pattern for API resilience. Services handle fetch, cache, retry, and expose typed data to panel components. Includes clear guidance on when to skip the circuit breaker for user-triggered one-shot calls versus background auto-polling services.

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RF Toolbox and RF Blockset in MATLAB -- S-parameter I/O, network conversions (S/Z/Y/ABCD/T/H/G, mixed-mode), cascade/de-embedding, rfbudget analysis, circuit composition, matching networks, amplifier stability, mixer spurs, rational fitting, SI channels, baseband processing, Circuit Envelope simulation. Trigger: sparameters, Touchstone, .s2p, .s4p, rfplot, smithplot, rfparam, rfwrite, zparameters, yparameters, abcdparameters, s2sdd, cascadesparams, deembedsparams, rfbudget, noise figure, OIP3, IIP3, amplifier, modulator, nport, rffilter, attenuator, seriesRLC, shuntRLC, lcladder, txline, circuit, setports, clone, matchingnetwork, stabilityk, stabilitymu, powergain, gammams, gammaml, mixerIMT, OpenIF, rational, rationalfit, stepresp, txlineWRLGC, rf.Amplifier, rf.Mixer, rf.Filter, rf.Sparameter, rfsystem, RF Blockset.

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Cascade PCB components, add lumped elements, export Touchstone, and bridge to eye diagram or antenna array workflows. TRIGGER: user asks to cascade or connect multiple RF PCB components, add lumped R/L/C, export S-parameters to Touchstone, or combine PCB elements into a circuit. Invoke BEFORE writing pcbcascade or circuit code — cascade rules and port matching are non-obvious. SKIP: designing individual components (use the specific matlab-design-pcb-* skill), EM analysis of a single component (use matlab-analyze-em), material/stackup setup only (use matlab-manage-pcb-material), optimization (use matlab-optimize-pcb-design).

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Quantum computing framework for building, simulating, optimizing, and executing quantum circuits. Use this skill when working with quantum algorithms, quantum circuit design, quantum simulation (noiseless or noisy), running on quantum hardware (Google, IonQ, AQT, Pasqal), circuit optimization and compilation, noise modeling and characterization, or quantum experiments and benchmarking (VQE, QAOA, QPE, randomized benchmarking).

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Acuity Scheduling integration. Manage Calendars, Clients, Users, Forms, Packages, Coupons. Use when the user wants to interact with Acuity Scheduling data.

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Think and work like an expert Integrated Circuit Designer. Use when a task calls for Integrated Circuit Designer judgment. Reasons from spec through Virtuoso schematic/layout, Calibre DRC/LVS/RCX, and foundry PDK corners across analog, mixed-signal, RF, and structured digital blocks; treats TT-only signoff, LVS-without-PEX, and common-centroid violations as first-class tapeout failure modes.

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Create, implement, or review legacy circuit mockups work with format, accessibility, performance, and visual-verification controls. Use when the requested deliverable depends on legacy circuit mockups.

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Systematic analysis of DC and AC linear circuits using Ohm's law, Kirchhoff's laws, node and mesh methods, Thevenin and Norton equivalents, phasor analysis, and Bode plots. Covers series and parallel reduction, superposition, source transformation, impedance in the frequency domain, first and second order transient response, and the conversion between time domain and phasor representations. Use when quantitatively predicting voltages, currents, power, gain, phase, or time response of any lumped-element linear circuit.

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Quantum computing framework for building, simulating, optimizing, and executing quantum circuits. Use this skill when working with quantum algorithms, quantum circuit design, quantum simulation (noiseless or noisy), running on quantum hardware (Google, IonQ, AQT, Pasqal), circuit optimization and compilation, noise modeling and characterization, or quantum experiments and benchmarking (VQE, QAOA, QPE, randomized benchmarking).

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Design combinational logic circuits from a functional specification through gate-level implementation. Covers AND, OR, NOT, XOR, NAND, NOR gates; NAND/NOR universality conversions; and standard building blocks including multiplexers, decoders, half/full adders, and ripple-carry adders. Use when translating a Boolean function or truth table into a hardware-realizable gate network and verifying it by exhaustive simulation.

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Implement circuit breaker logic for agentic tool calls — tracking tool health, transitioning between closed/open/half-open states, reducing task scope when tools fail, routing to alternatives via capability maps, and enforcing failure budgets to prevent error accumulation. Separates orchestration (deciding what to attempt) from execution (calling tools), following the expeditor pattern. Use when building agents that depend on multiple tools with varying reliability, designing fault-tolerant agentic workflows, recovering gracefully from tool outages mid-task, or hardening existing agents against cascading tool failures.

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Create, import, analyze, or resume an end-to-end Circuit Weaver electronic design with durable project state. Load the canonical workflow from skills/circuit-weaver/SKILL.md. Use kicad for one-off file inspection, bom for sourcing, and design-wizard only when explicitly requested.

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Building resilient distributed systems with circuit breakers, retries with full-jitter exponential backoff, retry budgets (per-request 3-attempt + per-client 10% ratio per Google SRE), deadline propagation, and the cascading-failure math (4 layers × 3 retries = 64x amplification). Grounded in Resilience4j, Microsoft Cloud Patterns, AWS Architecture Blog (Marc Brooker), and Google SRE Book.

日本語の概要は準備中です。原文の説明を表示しています。

Generate breadboard circuit mockups and visual diagrams using HTML5 Canvas drawing techniques. Use when asked to create circuit layouts, visualize electronic component placements, draw breadboard diagrams, mockup 6502 builds, generate retro computer schematics, or design vintage electronics projects. Supports 555 timers, W65C02S microprocessors, 28C256 EEPROMs, W65C22 VIA chips, 7400-series logic gates, LEDs, resistors, capacitors, switches, buttons, crystals, and wires.

日本語の概要は準備中です。原文の説明を表示しています。

Building resilient distributed systems with circuit breakers, retries with full-jitter exponential backoff, retry budgets (per-request 3-attempt + per-client 10% ratio per Google SRE), deadline propagation, and the cascading-failure math (4 layers × 3 retries = 64x amplification). Grounded in Resilience4j, Microsoft Cloud Patterns, AWS Architecture Blog (Marc Brooker), and Google SRE Book. NOT for server-side rate limiting, bulkhead isolation, backpressure protocols, or database-specific retry.

日本語の概要は準備中です。原文の説明を表示しています。