「drc」の検索結果

Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Every finding carries a confidence label and evidence source with trust_summary rollup. Analyzes PDF schematics from dev boards, reference designs, eval kits, and datasheets. Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb, .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal tracing, power budget, DFM, or wants to understand, debug, compare, or review any hardware design. Also for "check my board", "review before fab", "what's wrong with my schematic", "is this ready to order", "check my power supply", "verify this circuit", OSHWA certification readiness, or any electronics/PCB design question.

日本語の概要は準備中です。原文の説明を表示しています。

Analyze KiCad projects and PDF schematics: schematics, PCB layouts, Gerbers, footprints, symbols, netlists, and design rules. Reviews designs for bugs, traces nets, cross-references schematic to PCB, extracts BOM data, checks DRC/ERC, DFM, power trees, and regulator circuits. Every finding carries a confidence label and evidence source with trust_summary rollup. Analyzes PDF schematics from dev boards, reference designs, eval kits, and datasheets. Supports KiCad 5–10. Use whenever the user mentions .kicad_sch, .kicad_pcb, .kicad_pro, PCB design review, schematic analysis, PDF schematics, reference designs, Gerber files, DRC/ERC, netlist issues, BOM extraction, signal tracing, power budget, DFM, or wants to understand, debug, compare, or review any hardware design. Also for "check my board", "review before fab", "what's wrong with my schematic", "is this ready to order", "check my power supply", "verify this circuit", OSHWA certification readiness, or any electronics/PCB design question.

日本語の概要は準備中です。原文の説明を表示しています。

调用 Magic 8.3.641 执行 PD 操作：floorplan / place / DRC / layout extraction。触发场景：(1) bba-guru-pd 做 floorplan 与 placement；(2) routing 后做 DRC；(3) LVS 前 extract SPICE；(4) 显式 /bb-invoke-magic。

日本語の概要は準備中です。原文の説明を表示しています。

调用 KLayout 0.30.8 执行 GDSII 导出（stream out）、GDS-level DRC、或导出后 verify。PD 流程末尾产出最终 .gds（signoff 产物）。触发场景：(1) bba-guru-pd routed 后 GDS export；(2) GDS 层 DRC 检查；(3) 导出后 verify；(4) 显式 /bb-invoke-klayout。

日本語の概要は準備中です。原文の説明を表示しています。

Audit, finish, or port PCB placement and routing using circuit intent, mechanical constraints, sourcing evidence, native DRC/connectivity, rendered views, and manufacturing feedback. Use before routing, after autorouting, before fabrication release, when adapting a proven board to another connector, enclosure, platform, or regional variant, or when reviewing layers, GND references, power distribution, decoupling, buses, controlled interfaces, RF keepouts, vias, cost-driving features, opens, or DRC findings.

日本語の概要は準備中です。原文の説明を表示しています。

Expert-level VLSI design covering CMOS logic, custom layout, standard cell design, physical design flow, DRC, LVS, and advanced process nodes.

日本語の概要は準備中です。原文の説明を表示しています。

Generates a repo-specific orientation.md resource for the learning-opportunities skill. Invoke directly when the user asks for repo orientation; do not trigger automatically.

日本語の概要は準備中です。原文の説明を表示しています。

Facilitates deliberate skill development during AI-assisted coding. Offers interactive learning exercises after architectural work (new files, schema changes, refactors). Use when completing features, making design decisions, or when user asks to understand code better. Supports the user's stated goal of understanding design choices as learning opportunities.

日本語の概要は準備中です。原文の説明を表示しています。

Design review and validation workflow for KiCAD projects via MCP tools. Triggers on: "review my design", "check for errors", "audit", "DRC", "ERC", "find problems", "design review", "is this ready", "validate", "check my schematic", "check my PCB", "what's wrong", "run checks", "pre-fab review".

日本語の概要は準備中です。原文の説明を表示しています。

Check and compare software component versions on SageMaker HyperPod cluster nodes - NVIDIA drivers, CUDA toolkit, cuDNN, NCCL, EFA, AWS OFI NCCL, GDRCopy, MPI, Neuron SDK (Trainium/Inferentia), Python, and PyTorch. Use when checking component versions, verifying CUDA/driver compatibility, detecting version mismatches across nodes, planning upgrades, documenting cluster configuration, or troubleshooting version-related issues on HyperPod. Triggers on requests about versions, compatibility, component checks, or upgrade planning for HyperPod clusters.

日本語の概要は準備中です。原文の説明を表示しています。

通过本地 easyeda CLI、daemon 和连接器操作嘉立创EDA专业版（EasyEDA Pro）：依据需求与真实器件数据设计原理图、布局布线 PCB，并回读连接、几何、DRC 与保存结果。适用于已有工程操作及参数化电路设计。

日本語の概要は準備中です。原文の説明を表示しています。

Think and work like an expert Integrated Circuit Designer. Use when a task calls for Integrated Circuit Designer judgment. Reasons from spec through Virtuoso schematic/layout, Calibre DRC/LVS/RCX, and foundry PDK corners across analog, mixed-signal, RF, and structured digital blocks; treats TT-only signoff, LVS-without-PEX, and common-centroid violations as first-class tapeout failure modes.

日本語の概要は準備中です。原文の説明を表示しています。

从 MAS（io_ring/pad_list/clock_plan）+ 综合网表生成 Magic floorplan TCL，交给 bb-invoke-magic 执行。触发场景：(1) bba-guru-pd 综合后做 floorplan；(2) DRC 失败后调整 utilization 重生成；(3) 显式 /bb-create-floorplan。

日本語の概要は準備中です。原文の説明を表示しています。

Pin-to-net mapping auditor -- verifies that every IC pin in the schematic is connected to the correct net, matched against a pin map source of truth (CSV, datasheet table, or Python dict). Critical for BGA/QFN devices where swap errors are invisible to DRC/ERC.

日本語の概要は準備中です。原文の説明を表示しています。

Analyze existing KiCad projects, schematics, PCB layouts, Gerbers, netlists, and PDF reference schematics. Use when files such as .kicad_sch, .kicad_pcb, .kicad_pro, or Gerbers are supplied and the user wants review, debugging, net tracing, ERC/DRC/DFM, schematic-to-PCB comparison, or pre-fabrication checks. Do not use to create a new design from requirements or for standalone sourcing and ordering.

日本語の概要は準備中です。原文の説明を表示しています。

From a KiCad board to a parametric enclosure that fits it: ERC and DRC clean, board dimensions extracted, an OpenSCAD case with your clearance, Gerbers exported, fab hand-off only after GO. Use for "PCB to enclosure", "case for this board", "KiCad to OpenSCAD case".

日本語の概要は準備中です。原文の説明を表示しています。

Use when designing electrical schematics, PCB layouts, KiCad projects, or OpenSCAD enclosures — trace geometry, impedance, stackup, DFM/DRC/ERC sign-off, and hardware-software co-design boundaries.

日本語の概要は準備中です。原文の説明を表示しています。