Design, audit, or correct an electronic circuit from a product brief, native schematic, netlist, block diagram, or circuit description. Use for architecture and component-function review, power and logic-domain checks, reset and boot sequencing, bus ownership, ratings, timing, protection, safe states, component suitability, circuit bugs, or layout-facing electrical constraints.
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Treat readability and electrical correctness as separate gates. Default to review-only unless the user asks to change the authoritative circuit source.
Read references/circuit-audit-checklist.md
and produce .pcba-workflow/circuit-review.md from
assets/circuit-review.md.
[SPEC], [TARGET], or [TBD-MEASURE].
Include data/edge rate, topology and stubs, return plane, skew intent, current
allocation, placement, keepout, and authoritative source where applicable.For each change, state the defect and evidence, edit the source of truth, render the complete schematic, inspect it visually, rerun ERC/lint, compare canonical connectivity, and confirm protected layout files remain unchanged. A deliberate electrical change must appear explicitly in the connectivity delta and design decision record; do not hide it inside presentation cleanup.
Use PASS only when no critical/major issue or safety-relevant unknown remains
and the selected parts match the sourcing lock. Use USER_REVIEW for explicit
engineering decisions and BLOCKED for missing evidence or a failed check.
Hand drawing readability to $schematic-humanizer, part risk to
$qualify-pcba-sourcing, and placement/routing constraints to
$pcb-layout-review.
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Coordinate an evidence-gated electronic product and PCBA workflow from an idea, circuit description, schematic, netlist, PCB, BOM, or fabrication package through a reviewed order. Use for end-to-end requests, multi-stage hardware projects, workflow recovery, gate tracking, change invalidation, or deciding which specialist skill is required next.
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Operate and review a JLCPCB PCB/PCBA quote, optional physical-stencil request, or order using a frozen Gerber/drill, BOM, CPL, sourcing lock, constraints, and release manifest. Use for browser upload, board or stencil options, cost anomalies, coupons, component matching, substitutions, imported placement calibration, top/bottom preview inspection, cart preparation, or order records without silently accepting placement errors or payment.
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Audit, finish, or port PCB placement and routing using circuit intent, mechanical constraints, sourcing evidence, native DRC/connectivity, rendered views, and manufacturing feedback. Use before routing, after autorouting, before fabrication release, when adapting a proven board to another connector, enclosure, platform, or regional variant, or when reviewing layers, GND references, power distribution, decoupling, buses, controlled interfaces, RF keepouts, vias, cost-driving features, opens, or DRC findings.
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Turn an electronic product idea, behavior description, reverse-engineering note, or incomplete circuit concept into a decision-ready engineering brief and architecture. Use before schematic design or audit when functions, operating states, power, interfaces, mechanics, production quantity, cost, or measurable requirements are missing or ambiguous.
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Verify a PCBA BOM and proposed components before circuit or placement freeze, including exact manufacturer part numbers, pin semantics, packages, footprints, CAD and 3D models, lifecycle, live stock, MOQ, assembly class, price, and approved substitutes. Use for sourcing locks, unavailable or expensive parts, JLCPCB/LCSC matching, BOM risk, or cost-aware substitution decisions.
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Build and verify a vendor-neutral PCB/PCBA manufacturing release from one frozen design revision. Use when generating or auditing Gerber, drill, IPC-2581/ODB++, BOM, CPL/pick-and-place, assembly drawings, constraints, renders, DFM evidence, hashes, or release manifests, and when preventing mixed-revision fabrication or assembly uploads.
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