<一句话说清『这个 skill 做什么 + 何时调用』。把最关键的触发场景放最前面。结尾给 2-3 个用户会说的关键词。>
The English summary is being prepared. Showing the original description.
调用 Netgen 1.5.275 做 LVS 对比:综合网表 vs Magic 提取的 SPICE,必须 match 才能 signoff。触发场景:(1) bba-guru-pd extract 后做 LVS;(2) 显式 /bb-invoke-netgen。
The English summary is being prepared. Showing the original description.
See how to installReview the instructions the agent will receive before you install.
对比 schematic netlist(综合 netlist.v)与 layout netlist(Magic extracted.spice),输出 LVS 报告,必须 match。
bba-guru-pdbb-invoke-magic(action=extract)| arg | type | required | 说明 |
|---|---|---|---|
| schematic_netlist | path | true | designs/<name>/synth/netlist.v |
| layout_netlist | path | true | designs/<name>/pd/extracted.spice |
| tech_file | path | true | ASAP7 netgen setup file(.tcl) |
| top_module | string | true | — |
| design_name | string | true | — |
| stamp | string | false | <auto YYYYMMDD-HHMMSS> |
| field | 值 |
|---|---|
artifact_path | designs/<name>/pd/lvs_report.txt |
log_path | designs/<name>/pd/netgen_<stamp>.log |
match | bool("Circuits match uniquely") |
discrepancies | [{kind, instance, schematic, layout}] |
valid | bool |
error | string|null |
scripts/render_netgen.py 生成 batch 命令:
netgen -batch lvs \
"designs/<name>/pd/extracted.spice <top>" \
"designs/<name>/synth/netlist.v <top>" \
<tech_file> \
designs/<name>/pd/lvs_report.txt
scripts/run_netgen.py:
source ~/wrk/eda_opensources/eda_env.shnetgen -batch lvs --version 2>&1 | grep "1.5" 否则 VERSION_MISMATCHtimeout 600 netgen -batch lvs <args> > <log> 2>&1exit:<rc>scripts/parse_lvs.py 扫描 lvs_report.txt:
Circuits match uniquely. → match=trueCircuits differ → match=false,提取后续 Net mismatch / Device mismatch 段为 discrepancies写 lvs_<stamp>.json。
返回 JSON。bba-guru-pd:
bb-invoke-opensta(mode=post_pd)synth-needs-fix| 状态 | 行动 |
|---|---|
| match=true | 进 post-PD STA |
| match=false | 开 synth-needs-fix |
VERSION_MISMATCH | 修 eda_env.sh |
| Phase 2 timeout(600s) | error="LVS_TIMEOUT" |
scripts/render_netgen.py、scripts/run_netgen.py、scripts/parse_lvs.pyreferences/asap7_netgen_setup.md — setup file 与 device mapGotcha/lvs_pitfalls.md — 黑盒、port order、电源 net 命名No reviews yet. Tell others what you thought.
No login needed. Share how it worked for you, ask a question, or note where it did not run.
No comments yet. Be the first to write one.
<一句话说清『这个 skill 做什么 + 何时调用』。把最关键的触发场景放最前面。结尾给 2-3 个用户会说的关键词。>
The English summary is being prepared. Showing the original description.
从粗略 idea 设计芯片或功能模块架构,输出专业架构文档到 spec_arch 目录。Trigger: 芯片架构设计, IC架构, 电路模块设计, 硬件架构. Generate IC/Chip architecture specification from rough ideas.
The English summary is being prepared. Showing the original description.
基于 AST 检查 CDC/RDC 违例:对比 MAS clock_domains 找跨域信号,检查是否被 2ff-sync CBB 保护。触发场景:(1) bba-guru-synthesis 综合前;(2) 显式 /bb-check-cdc。
The English summary is being prepared. Showing the original description.
调用 babel-lsp / verible-verilog-lint 检查 SV 源码。src 必须可综合(零 syntax error),tb 允许 verification constructs。发现 src error 时自动修复重检(max 3 iter)。触发:(1) bba-guru-rtl 生成后;(2) RTL 修复重检;(3) 显式 /bb-check-lint。
The English summary is being prepared. Showing the original description.
Babel internal issue protocol — close a handoff after downstream agent picked it up or user signed off. Moves designs/<name>/.handoff/<label>.md to .handoff/closed/ (using mv per CLAUDE.md), appends to handoff_log.jsonl.
The English summary is being prepared. Showing the original description.
对抗性代码评审:代码质量 / 可维护性 / 时序风险 / 综合友好度 / MAS 对齐度。默认 ruthless 模式,找 EVERY flaw。触发场景:(1) RTL lint 后;(2) 显式 /bb-code-review。
The English summary is being prepared. Showing the original description.