「manufacturing」の検索結果

Expert-level manufacturing processes covering machining, casting, forming, welding, additive manufacturing, tolerances, and process selection.

日本語の概要は準備中です。原文の説明を表示しています。

Knowledge base from the DoD Manufacturing Readiness Level (MRL) Deskbook (Version 2022, OSD ManTech / Joint Service–Industry MRL Working Group). Use for assessing and managing manufacturing maturity and producibility risk in defense acquisition: the 10-level MRL scale and its non-linear, target-not-grade nature; the five demonstration environments (laboratory → production-relevant → production-representative → pilot line → production line); the nine manufacturing-risk threads and sub-threads; how MRL targets map onto Adaptive Acquisition Framework milestones (MRL 4/6/7/8/9); conducting an MRL Assessment; building a Manufacturing Maturation Plan; putting MRL maturity into contract language (Section L/M, SOW, AS6500A, DIDs); tailoring criteria for S&T, single-system, ship, sustainment, and industry contexts; and screening operational-technology cybersecurity. Manufacturing-readiness focused — it measures producibility risk and frames mitigation; it is NOT a technology-readiness (TRL) guide, a full systems-engineering process model, a cost-estimating or schedule guide, or a deep cybersecurity audit method (see sibling packs for those).

日本語の概要は準備中です。原文の説明を表示しています。

Knowledge base from the DoD M&Q BoK (the Manufacturing and Quality Engineering Body of Knowledge), v3.0 of July 2025, published by OUSD(R&E). Use for the manufacturing-and-quality view of the defense acquisition life cycle: what M&Q engineers do across the Adaptive Acquisition Framework phases (Pre-MDD, Materiel Solution Analysis, Technology Maturation and Risk Reduction, Engineering and Manufacturing Development, Production and Deployment, Operations and Support); the twelve M&Q threads (A–L) built on the '5 Ms'; manufacturing feasibility and producibility; Manufacturing Readiness Levels and assessments; Key/Critical Characteristics and process capability (Cp/Cpk, SPC); the standards stack (AS6500, AS9100/ISO 9001, AS9103, AS9145); technical reviews (ASR/PDR/CDR/PRR) and milestone gates; DCMA surveillance; industrial base and supply chain; and sustainment (LCSP, IPS, ILA, ISR). Scope is DoD acquisition M&Q practice on the Major Capability Acquisition path — it is a best-practice compilation, not policy, and is thin on detailed shop-floor process engineering, contract law, and the full text of the cited industry standards (which it names but does not reproduce).

日本語の概要は準備中です。原文の説明を表示しています。

I am a veteran print production specialist with 15+ years in tabletop game manufacturing. I've shepherded hundreds of games from digital files to retail-ready products, working with manufacturers from The Game Crafter to Panda GM to Cartamundi. My expertise spans the entire production pipeline: color management, dieline creation, paper selection, finishing techniques, component nesting, insert design, and the critical art of the unboxing experience. I've learned the hard way about RGB-to-CMYK disasters, registration drift, humidity warp, and minimum font sizes that become illegible smudges. I know the difference between 280gsm blue-core and 320gsm black-core card stock by feel. I can tell you why your rich black needs to be C60-M40-Y40-K100, not just K100. I understand why your box needs 15mm clearance on each dimension, and why that gorgeous neon green in your design will become a muddy olive in print. Use when "print my game, packaging design, prepare files for print, dieline, print specifications, board game manufacturing, card game printing, box design, bleed and safe area, CMYK conversion, paper stock, card finish, foil stamping, embossing, unboxing experience, thermoform insert, punchboard design, component manufacturing, Panda GM, Game Crafter, Cartamundi, print-production, packaging, manufacturing, board-games, card-games, cmyk, dieline, die-cutting, offset-printing, tabletop" mentioned.

日本語の概要は準備中です。原文の説明を表示しています。

工場の設備・人員・材料・納期を踏まえて生産順序を組み、段取り替えや工程間の負荷を調整し、設備故障や材料不足時の計画見直しを支援するスキル。

• 限られた設備での生産順序の検討
• 設備故障後に計画を組み直したいとき
• ロット量と段取り替え費用の比較

Industrial AI literature research with mandatory intake questions, venue-aware source prioritization, structured report outputs, and survey draft generation. Use when the user needs up-to-date research on predictive maintenance, intelligent scheduling, industrial anomaly detection, smart manufacturing, cyber-physical systems, edge AI for automation, or crossover robotics-for-industry topics. Also trigger for adjacent terms: "digital twin", "industrial IoT", "Industry 4.0", "manufacturing AI", "factory automation", "process optimization", or "survey draft" in industrial contexts.

日本語の概要は準備中です。原文の説明を表示しています。

Think and work like an expert Manufacturing Engineer. Use when a task calls for Manufacturing Engineer judgment. Reasons from process physics, capability, and cost through Shercliff-Lovatt process selection, ASME Y14.5 GD&T, CAM simulation, and AIAG APQP/PPAP with MSA-gated SPC capability, treating high %GRR masquerading as variation, false Cpk on unstable or short runs, datum-scheme mismatch, and uncontrolled ECN tweaks as first-class failure modes.

日本語の概要は準備中です。原文の説明を表示しています。

Think and work like an expert Additive Manufacturing Engineer. Use when a task calls for Additive Manufacturing Engineer judgment. Reasons from melt-pool physics, VED, and thermal history through LPBF vs DED process selection, build orientation anisotropy, support design, powder lot control, CT/metallography NDE, and ASTM F42 / ISO-ASTM 529xx qualification—not generic 3D printing.

日本語の概要は準備中です。原文の説明を表示しています。

製造現場の規格不適合について、対象品の隔離から原因分析、処置の検討、是正・予防措置の効果確認までを整理し、管理図の読み取りや仕入先品質の改善も支援します。

• 検査で見つかった不適合を調査したいとき
• 根本原因の分析手法を選びたいとき
• 是正措置の計画作成と効果確認

JLCPCB PCB fabrication and assembly — BOM/CPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber/CPL export, stencil ordering, and BOM management, see the `bom` skill.

日本語の概要は準備中です。原文の説明を表示しています。

JLCPCB PCB fabrication and assembly — BOM/CPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber/CPL export, stencil ordering, and BOM management, see the `bom` skill.

日本語の概要は準備中です。原文の説明を表示しています。

Export pcbComponent designs to Gerber files with RF connectors and fab service formatting for PCB manufacturing. TRIGGER: user asks to export a PCB design to Gerber, generate manufacturing files, or write out a pcbComponent for fabrication. Invoke BEFORE writing export code — gerberWrite signature (pcbComponent, connectors, filename) is non-obvious. SKIP: importing/reading PCB files (use matlab-read-pcb-layout), building PCB geometry (use matlab-assemble-pcb-layout), EM analysis (use matlab-analyze-em), material/stackup setup (use matlab-manage-pcb-material).

日本語の概要は準備中です。原文の説明を表示しています。

Manufacturing and fabrication workflow for KiCAD projects via MCP tools. Triggers on: "send to fab", "order boards", "gerbers", "JLCPCB", "manufacturing", "export for production", "pick and place", "assembly files", "generate fabrication outputs", "BOM for fab", "production files", "fab house".

日本語の概要は準備中です。原文の説明を表示しています。

Design and implement discrete event simulations (DES) for systems where state changes occur at discrete time points: queues, manufacturing, logistics, networks. Use when "discrete event, DES simulation, queuing system, queue model, manufacturing simulation, process simulation, SimPy, event-driven simulation, " mentioned.

日本語の概要は準備中です。原文の説明を表示しています。

Designing tabletop games - from core mechanics to manufacturing, from prototyping to KickstarterUse when "board game, tabletop, card game, worker placement, deck building, area control, playtesting, rulebook, kickstarter game, game balance, asymmetric factions, euro game, ameritrash, party game, dice game, prototype, game publisher, crowdfunding game, board-games, tabletop, game-design, mechanics, playtesting, kickstarter, manufacturing, rulebook, components, balance, player-interaction" mentioned.

日本語の概要は準備中です。原文の説明を表示しています。

半导体芯片制造工艺 (Semiconductor Process Engineering / 半导体芯片制造工艺 — 以「物理化学极限 + 良率经济双重约束」为特征的集成电路前道/后道制造工艺认知操作系统：从「器件架构与微缩路线（planar→FinFET→GAA nanosheet→CFET、等效微缩 DTCO/STCO、背面供电 BSPDN）→ 工艺整合（FEOL/MOL/BEOL 模块协同、PDK、流片 tape-out）→ 单元工艺（光刻 litho（DUV 浸没式 193i / EUV 13.5nm / 多重曝光 SADP-SAQP / OPC / mask）、刻蚀 etch（RIE/ICP/原子层刻蚀 ALE）、薄膜沉积 depo（CVD/PECVD/LPCVD/ALD/PVD/外延 epi/电镀 Cu）、掺杂 doping（离子注入 ion implant / 退火 RTA-laser anneal）、CMP 化学机械抛光、清洗 cleaning）→ 量测检测 metrology（CD-SEM / OCD / overlay / 椭偏 ellipsometry / 缺陷检测 defect inspection / e-beam）→ 良率工程 yield（缺陷密度 / SPC 统计过程控制 / FDC / APC / DOE 实验设计 / 良率爬坡 yield ramp）→ 先进封装 advanced packaging（2.5D/3D、CoWoS、HBM、混合键合 hybrid bonding、chiplet、TSV）」的完整器件-工艺-良率-量产决策链。覆盖 (a) 第一性张力 — **物理/化学/材料的硬约束（量子隧穿、短沟道效应、RC 延迟、热预算、缺陷物理、ppb 级污染控制）⇄ 良率/成本/产能的经济约束（每片晶圆成本、良率是主经济指标、D0 缺陷密度、wafer-per-hour、折旧）**；**持续微缩/摩尔定律（dimensional + equivalent scaling、节点路线图 N5/N3/N2/A16/A14、high-NA EUV）⇄ 物理极限/微缩放缓（原子尺度、漏电、功耗墙、成本墙、'摩尔定律已死'之争）**；**协同优化/整合（DTCO 设计-工艺协同、STCO 系统-工艺协同、模块间 trade-off）⇄ 单模块极致优化（单一 unit process 工艺窗口）**；**工艺配方的 tacit 手艺（process recipe 调试、工艺窗口、缺陷根因分析、量产 ramp 的经验）⇄ 可建模/可仿真/数据驱动（TCAD 仿真、ML 良率分析、APC/FDC、数字孪生）**；**性能-功耗-面积-成本 PPAC 四角权衡 ⇄ 良率/可制造性 DFM 优先**；**自主可控/国产替代（卡脖子、EUV 出口管制、设备/材料/EDA 国产化、SMIC/长江存储/长鑫/中微/北方华创/上海微电子）⇄ 全球高度分工（ASML 光刻垄断、AMAT/Lam/TEL/KLA 设备、TSMC/Samsung/Intel 代工、全球供应链）**。(b) 核心工作流 / pipeline（最标准、最易蒸高质量 + CLI 化）— 新节点/新工艺导入：器件目标与 PPAC 定义 → 工艺整合方案与 PDK → 单元工艺开发与配方调试（DOE 找工艺窗口）→ 量测建立与 SPC → 良率爬坡（缺陷分类 + 根因分析 + 工艺改善）→ 量产移交与持续改善。具体单元工艺 SOP：光刻（曝光条件 / OPC / overlay 控制 / 多重曝光分解）、刻蚀（选择比 / profile / loading effect / ALE）、沉积（台阶覆盖 / 应力 / 均匀性）、CMP（去除速率 / 碟形 dishing / 侵蚀 erosion）、量测与缺陷分析、良率分析与 FA 失效分析。(c) 工具栈 — 设备（光刻 ASML/上海微电子 SMEE；刻蚀+沉积 AMAT/Lam/TEL/中微 AMEC/北方华创 Naura；离子注入 AMAT/Axcelis；CMP AMAT/荏原 Ebara；量测检测 KLA/AMAT/中科飞测/上海精测）、EDA/TCAD/仿真（Synopsys Sentaurus/Silvaco/Coventor SEMulator3D、OPC Calibre/Synopsys）、良率与制造软件（SPC、MES、FDC/APC、缺陷分析 yield management、PWS）、材料（光刻胶 photoresist、CMP 浆料 slurry、特气、靶材、掩膜 mask blank）。(d) 知识正典 — 半导体工艺 canon 横跨器件物理与制造工程：核心教材（Plummer/Deal/Griffin《Silicon VLSI Technology》、Sze《Physics of Semiconductor Devices》《VLSI Technology》、Wolf & Tauber《Silicon Processing for the VLSI Era》、Campbell《Fabrication Engineering at the Micro and Nanoscale》、May & Spanos《Fundamentals of Semiconductor Manufacturing and Process Control》、Quirk & Serda《Semiconductor Manufacturing Technology》、肖国勇/施敏中文教材）、路线图（ITRS/IRDS、IEEE 国际器件与系统路线图）、顶会论文（IEDM、Symposium on VLSI Technology、IRPS 可靠性、SPIE Advanced Lithography、ISSCC、DAC）、行业分析（SemiAnalysis、TechInsights、IC Knowledge）。(e) figures/流派 — 学术与器件奠基（Gordon Moore 摩尔、Robert Dennard 登纳德微缩、胡正明 Chenming Hu FinFET/UTB-SOI 发明人 UC Berkeley、刘明 Tsu-Jae King Liu Berkeley、Krishna Saraswat Stanford、Mark Bohr Intel 工艺架构）、产业领袖与工艺大师（张忠谋 Morris Chang TSMC、林本坚 Burn-Jeng Lin 浸没式光刻、Martin van den Brink ASML、米玉杰/梁孟松 SMIC/三星工艺、Mark Liu/魏哲家 TSMC）、行业分析师（Dylan Patel SemiAnalysis、Scotten Jones IC Knowledge、TechInsights 拆解、Handel Jones）、科普与拆解（Asianometry、The Chip Letter、半导体行业观察）。流派分歧：等效微缩派 vs 摩尔定律已死派、前道微缩 vs 先进封装 chiplet 异构集成、dimensional scaling vs DTCO 协同优化、IDM vs 纯代工 foundry 模式、自主可控/国产替代路线 vs 全球分工。(f) 行业话术/黑话 — 制程节点 node / 流片 tape-out / 工艺窗口 process window / 良率 yield / 缺陷密度 D0 / 关键尺寸 CD / 套刻 overlay / 掩膜 reticle-mask / 光刻胶 PR / 浸没式 immersion / EUV/DUV / 多重曝光 multi-patterning SADP-SAQP / OPC / 刻蚀选择比 selectivity / profile / loading effect / 原子层刻蚀 ALE / 台阶覆盖 step coverage / 外延 epi / 离子注入 implant / 退火 anneal / RTA / CMP / dishing-erosion / FEOL-MOL-BEOL / FinFET / GAA / 纳米片 nanosheet / CFET / 背面供电 BSPDN / high-NA / PPAC / DTCO-STCO / DFM / SPC / FDC-APC / DOE / WAT-PCM / 良率爬坡 yield ramp / FA 失效分析 / particle 颗粒 / 洁净室 cleanroom-级别 / 12寸-8寸 wafer / chiplet / CoWoS / HBM / 混合键合 hybrid bonding / TSV / PDK / 等效微缩. (g) 争议/批判 — 「摩尔定律是否已死 vs 等效微缩继续」、「节点命名营销化（N3/N2 ≠ 物理 3nm/2nm，gate pitch/metal pitch 才是真尺度）」、「前道微缩 vs 先进封装异构集成谁是未来」、「自主可控/国产替代的现实（EUV 卡脖子、设备/材料/EDA 国产化进度、出口管制 entity list、良率与成熟度差距）」、「良率/成本/性能三角权衡」、「人才稀缺与工艺 know-how 的 tacit 性」、「中国大基金/产能扩张是否过剩」、「制裁与技术封锁」。(h) 大量隐性工艺手艺（process recipe 调试与工艺窗口寻找、缺陷根因分析与 FA、量产良率爬坡的经验判

日本語の概要は準備中です。原文の説明を表示しています。

Use this skill whenever reasoning about manufacturing, scaling production, pricing strategies, operational efficiency, vertical integration, or labor compensation. Trigger this skill for situations involving hardware development, supply chain optimization, mass-market economics, or when a founder is deciding between outside investment and bootstrapping. Apply Henry Ford's principles of absolute operational control, continuous manufacturing improvement, and treating efficiency as a service to the consumer. Reach for this whenever a user is building physical products, scaling a business for the 'great multitude', or trying to eliminate operational waste.

日本語の概要は準備中です。原文の説明を表示しています。

Codified expertise for production scheduling, job sequencing, line balancing, changeover optimization, and bottleneck resolution in discrete and batch manufacturing. Informed by production schedulers with 15+ years experience. Includes TOC/drum-buffer-rope, SMED, OEE analysis, disruption response frameworks, and ERP/MES interaction patterns. Use when scheduling production, resolving bottlenecks, optimizing changeovers, responding to disruptions, or balancing manufacturing lines.

日本語の概要は準備中です。原文の説明を表示しています。

Use whenever the user wants to find, shortlist, vet, or enrich US engineering firms — civil, structural, MEP, mechanical, electrical, geotechnical, transportation, environmental, and manufacturing. **For real-world engineering (buildings, infrastructure, manufacturing) — NOT software engineering.** Triggers on "find civil engineering firms in Florida for transportation", "shortlist three structural engineering firms with high-rise experience", "MEP consultancy for a hospital project", or "pull contact info for these 12 engineering firm domains", even when described indirectly (PE-stamped drawings, building-permit review). Drives the ServiceGraph API (api.servicegraph.co) — a 100k+ US firm catalog filterable by industry, services, location, size, ratings. Defer software-dev / "engineering team" / SaaS-architecture asks to find-software-developer. Skip in-house engineering-manager hires, DIY questions, software-product comparisons (Revit, AutoCAD), non-US firms, individual freelancers.

日本語の概要は準備中です。原文の説明を表示しています。

JLCPCB PCB fabrication and assembly — BOM/CPL generation, basic vs extended parts, assembly constraints, design rules, ordering workflow. Use with KiCad for JLCPCB manufacturing. Use this skill when the user mentions JLCPCB, wants to order PCBs or assembled boards, needs prototype bare PCBs and stencils, wants to know JLCPCB design rules and capabilities, or is asking about PCB manufacturing costs or turnaround times. For gerber/CPL export, stencil ordering, and BOM management, see the `bom` skill.

日本語の概要は準備中です。原文の説明を表示しています。

Prepare qualified Fusion CAM setups, operations, toolpaths and quarantined NC candidates using explicit manufacturing assets and authority. Never controls physical equipment.

日本語の概要は準備中です。原文の説明を表示しています。

Expert-level composites engineering covering fiber reinforced polymers, matrix materials, laminate theory, manufacturing processes, failure modes, and composite design.

日本語の概要は準備中です。原文の説明を表示しています。

When the user wants to optimize aerospace and defense supply chains, manage long lead-time components, handle MRO operations, or ensure AS9100 compliance. Also use when the user mentions "aerospace supply chain," "aviation manufacturing," "MRO supply chain," "AS9100," "aircraft parts," "defense procurement," "AOG support," "airworthiness," "ITAR compliance," "aerospace certification," or "aviation aftermarket." For general manufacturing, see production-scheduling. For quality, see quality-management.

日本語の概要は準備中です。原文の説明を表示しています。

Codified expertise for production scheduling, job sequencing, line balancing, changeover optimization, and bottleneck resolution in discrete and batch manufacturing. Informed by production schedulers with 15+ years experience. Includes TOC/drum-buffer-rope, SMED, OEE analysis, disruption response frameworks, and ERP/MES interaction patterns. Use when scheduling production, resolving bottlenecks, optimizing changeovers, responding to disruptions, or balancing manufacturing lines.

日本語の概要は準備中です。原文の説明を表示しています。